Techniques for memory access prefetching using workload data

ABSTRACT

Various embodiments are generally directed to an apparatus, method and other techniques for prefetching data for a workload based on memory access information of the workload. For example, an apparatus may include at least one memory, at least one processor, and logic, at least a portion of the logic comprised in hardware, the logic to determine a workload to be executed via the at least one processor, monitor a plurality of memory accesses of the at least one memory by the workload during execution, and generate memory access information for the workload. Other embodiments are described.

CROSS-REFERENCE TO RELATED CASES

This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and United Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments described herein generally include prefetching data for execution of a workload based on memory access information associated with the workload.

BACKGROUND

A computing data center may include one or more computing systems including a plurality of compute nodes that may include various compute structures (e.g., servers or sleds) and may be physically located on multiple racks. The sleds may include a number of physical resources interconnected via one or more compute structures and buses. Moreover, the sleds may be interconnected with other sleds via networking connections. Typically, compute structures may include processor devices operable to execute various workloads for performing various functions. Embodiments discussed herein are directed to solving these and other problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates an example of a data center.

FIG. 2 illustrates an example of a rack.

FIG. 3 illustrates an example of a data center.

FIG. 4 illustrates an example of a data center.

FIG. 5 illustrates an example of a switching infrastructure.

FIG. 6 illustrates an example of a data center.

FIG. 7 illustrates an example of a sled.

FIG. 8 illustrates an example of a data center.

FIG. 9 illustrates an example of a data center.

FIG. 10 illustrates an example of a sled.

FIG. 11 illustrates an example of a data center.

FIG. 12 illustrates an embodiment of a first operating environment.

FIG. 13 illustrates an embodiment of a second operating environment.

FIG. 14 illustrates an embodiment of a third operating environment.

FIG. 15 illustrates an embodiment of a fourth operating environment.

FIG. 16 illustrates an embodiment of a fifth operating environment.

FIG. 17 illustrates an example of a first logic flow diagram.

FIG. 18 illustrates an example of a second logic flow diagram.

FIG. 19 illustrates an example of a third logic flow diagram.

FIG. 20 illustrates an example of a fourth logic flow diagram.

DETAILED DESCRIPTION

Various embodiments may be generally directed to determining memory access information associated with workloads to be executed by a computing system processing device. In general, a workload may include any process associated with a memory operation, such as a memory read, a memory write, a memory remove, a memory allocate, a memory deallocate, a memory format, a memory cleanup, or any other type of memory operation. Non-limiting examples of workloads may include, without limitation, an application, a thread, communication traffic (for instance, packet processing), and/or the like. The memory access information may be used by the processing device to make intelligent prefetch decisions when executing the workloads. As previously mentioned, conventional compute structures currently are not able to obtain detailed memory access information for each particular workload being executed via processing devices of the compute structure. Accordingly, the processor devices are not able to efficiently and effectively make intelligent decisions for accessing data when executing the workloads. Thus, embodiments discussed herein are directed to solving these and other problems.

For example, embodiments discussed herein may include circuitry to monitor workload behavior. A non-limiting example of workload behavior may include memory operations. The circuitry may process the workload behavior to generate memory access information for a workload. The memory access information may be stored in a memory unit operably coupled to the circuitry, for instance, in an access pattern data store. In another example, a workload may include memory access information, for instance, configured as a prefetch header. Accordingly, a workload may include a data element having memory access information that may be provided to a processing device executing the workload. In general, the memory access information may include any information relating to memory accesses performed during execution of a workload. In some embodiments, memory access information may include information relating to the data and/or areas of memory accessed by a workload. In various embodiments, the memory access information may be used to prefetch data during execution of the workload to, among other things, improve processing device efficiency and usage of memory resources. Embodiments are not limited in this manner and these other details will become apparent in the following discussion.

Reference is now made to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives consistent with the claimed subject matter.

FIG. 1 illustrates a conceptual overview of a data center 100 that may generally be representative of a data center or other type of computing network in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 1, data center 100 may generally contain a plurality of racks, each of which may house computing equipment comprising a respective set of physical resources. In the particular non-limiting example depicted in FIG. 1, data center 100 contains four racks 102A to 102D, which house computing equipment comprising respective sets of physical resources (PCRs) 105A to 105D. According to this example, a collective set of physical resources 106 of data center 100 includes the various sets of physical resources 105A to 105D that are distributed among racks 102A to 102D. Physical resources 106 may include resources of multiple types, such as—for example—processors, co-processors, accelerators, field-programmable gate arrays (FPGAs), memory, and storage. The embodiments are not limited to these examples.

The illustrative data center 100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In particular, in the illustrative embodiment, the sleds are shallower than typical printed circuit boards (PCBs). In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the PCBs. Further, the components on the sled are spaced further apart than in typical circuit PCBs, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while memory modules are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

Furthermore, in the illustrative embodiment, the data center 100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures which may be in accordance to standards, such as Institute of Electrical and Electronics Engineers (IEEE) 802.3-2015 standard (Ethernet) or any predecessors, revisions, or variants thereof, and other architectures, such as Intel® Omni-Path®. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twister pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center 100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. The illustrative data center 100 additionally receives usage information for the various resources, predicts resource usage for different types of workloads based on past resource usage, and dynamically reallocates the resources based on this information.

The racks 102A, 102B, 102C, 102D of the data center 100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example, data center 100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulatable resource sleds. Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C, 102D include integrated power sources that receive higher current than typical for power sources. The increased current enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies. FIG. 2 illustrates an exemplary logical configuration of a rack 202 of the data center 100. As shown in FIG. 2, rack 202 may generally house a plurality of sleds, each of which may comprise a respective set of physical resources. In the particular non-limiting example depicted in FIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective sets of physical resources 205-1 to 205-4, each of which constitutes a portion of the collective set of physical resources 206 comprised in rack 202. With respect to FIG. 1, if rack 202 is representative of—for example—rack 102A, then physical resources 206 may correspond to the physical resources 105A comprised in rack 102A. In the context of this example, physical resources 105A may thus be made up of the respective sets of physical resources, including physical storage resources 205-1, physical accelerator resources 205-2, physical memory resources 204-3, and physical compute resources 205-5 comprised in the sleds 204-1 to 204-4 of rack 202. The embodiments are not limited to this example. Each sled may contain a pool of each of the various types of physical resources (e.g., compute, memory, accelerator, storage). By having robotically accessible and robotically manipulatable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate.

FIG. 3 illustrates an example of a data center 300 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. In the particular non-limiting example depicted in FIG. 3, data center 300 comprises racks 302-1 to 302-32. In various embodiments, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate various access pathways. For example, as shown in FIG. 3, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate access pathways 311A, 311B, 311C, and 311D. In some embodiments, the presence of such access pathways may generally enable automated maintenance equipment, such as robotic maintenance equipment, to physically access the computing equipment housed in the various racks of data center 300 and perform automated maintenance tasks (e.g., replace a failed sled, upgrade a sled). In various embodiments, the dimensions of access pathways 311A, 311B, 311C, and 311D, the dimensions of racks 302-1 to 302-32, and/or one or more other aspects of the physical layout of data center 300 may be selected to facilitate such automated operations. The embodiments are not limited in this context.

FIG. 4 illustrates an example of a data center 400 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 4, data center 400 may feature an optical fabric 412. Optical fabric 412 may generally comprise a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled in data center 400 can send signals to (and receive signals from) each of the other sleds in data center 400. The signaling connectivity that optical fabric 412 provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks. In the particular non-limiting example depicted in FIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to 402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and 404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example, data center 400 comprises a total of eight sleds. Via optical fabric 412, each such sled may possess signaling connectivity with each of the seven other sleds in data center 400. For example, via optical fabric 412, sled 404A-1 in rack 402A may possess signaling connectivity with sled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2, 404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the other racks 402B, 402C, and 402D of data center 400. The embodiments are not limited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that may generally be representative of link-layer connectivity that may be established in some embodiments among the various sleds of a data center, such as any of example data centers 100, 300, and 400 of FIGS. 1, 3, and 4. Connectivity scheme 500 may be implemented using an optical fabric that features a dual-mode optical switching infrastructure 514. Dual-mode optical switching infrastructure 514 may generally comprise a switching infrastructure that is capable of receiving communications according to multiple link-layer protocols via a same unified set of optical signaling media, and properly switching such communications. In various embodiments, dual-mode optical switching infrastructure 514 may be implemented using one or more dual-mode optical switches 515. In various embodiments, dual-mode optical switches 515 may generally comprise high-radix switches. In some embodiments, dual-mode optical switches 515 may comprise multi-ply switches, such as four-ply switches. In various embodiments, dual-mode optical switches 515 may feature integrated silicon photonics that enable them to switch communications with significantly reduced latency in comparison to conventional switching devices. In embodiments, the dual-mode switch may be a single physical network wire that may be capable of carrying Ethernet or Omni-Path communication, which may be auto-detected by the dual-mode optical switch 515 or configured by the Pod management controller. This allows for the same network to be used for Cloud traffic (Ethernet) or High Performance Computing (HPC), typically Omni-Path or Infiniband. Moreover, and in some instances, an Omni-Path protocol may carry Omni-Path communication and Ethernet communication. In some embodiments, dual-mode optical switches 515 may constitute leaf switches 530 in a leaf-spine architecture additionally including one or more dual-mode optical spine switches 520. Note that in some embodiments, the architecture may not be a leaf-spine architecture, but may be a two-ply switch architecture to connect directly to the sleds.

In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP packets) and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel®'s Omni-Path Architecture®'s, Infiniband®) via optical signaling media of an optical fabric. As reflected in FIG. 5, with respect to any particular pair of sleds 504A and 504B possessing optical signaling connectivity to the optical fabric, connectivity scheme 500 may thus provide support for link-layer connectivity via both Ethernet links and HPC links. Thus, both Ethernet and HPC communications can be supported by a single high-bandwidth, low-latency switch fabric. The embodiments are not limited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 that may be representative of an architecture of any particular one of the racks depicted in FIGS. 1 to 4 according to some embodiments. As reflected in FIG. 6, rack architecture 600 may generally feature a plurality of sled spaces into which sleds may be inserted, each of which may be robotically-accessible via a rack access region 601. In the particular non-limiting example depicted in FIG. 6, rack architecture 600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5 feature respective multi-purpose connector modules (MPCMs) 616-1 to 616-5. In some instances, when a sled is inserted into any given one of sled spaces 603-1 to 603-5, the corresponding MPCM may couple with a counterpart MPCM of the inserted sled. This coupling may provide the inserted sled with connectivity to both signaling infrastructure and power infrastructure of the rack in which it is housed.

Included among the types of sleds to be accommodated by rack architecture 600 may be one or more types of sleds that feature expansion capabilities. FIG. 7 illustrates an example of a sled 704 that may be representative of a sled of such a type. As shown in FIG. 7, sled 704 may comprise a set of physical resources 705, as well as an MPCM 716 designed to couple with a counterpart MPCM when sled 704 is inserted into a sled space such as any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may also feature an expansion connector 717. Expansion connector 717 may generally comprise a socket, slot, or other type of connection element that is capable of accepting one or more types of expansion modules, such as an expansion sled 718. By coupling with a counterpart connector on expansion sled 718, expansion connector 717 may provide physical resources 705 with access to supplemental computing resources 705B residing on expansion sled 718. The embodiments are not limited in this context.

FIG. 8 illustrates an example of a rack architecture 800 that may be representative of a rack architecture that may be implemented in order to provide support for sleds featuring expansion capabilities, such as sled 704 of FIG. 7. In the particular non-limiting example depicted in FIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7, which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to 803-7 include respective primary regions 803-1A to 803-7A and respective expansion regions 803-1B to 803-7B. With respect to each such sled space, when the corresponding MPCM is coupled with a counterpart MPCM of an inserted sled, the primary region may generally constitute a region of the sled space that physically accommodates the inserted sled. The expansion region may generally constitute a region of the sled space that can physically accommodate an expansion module, such as expansion sled 718 of FIG. 7, in the event that the inserted sled is configured with such a module.

FIG. 9 illustrates an example of a rack 902 that may be representative of a rack implemented according to rack architecture 800 of FIG. 8 according to some embodiments. In the particular non-limiting example depicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7, which include respective primary regions 903-1A to 903-7A and respective expansion regions 903-1B to 903-7B. In various embodiments, temperature control in rack 902 may be implemented using an air cooling system. For example, as reflected in FIG. 9, rack 902 may feature a plurality of fans 919 that are generally arranged to provide air cooling within the various sled spaces 903-1 to 903-7. In some embodiments, the height of the sled space is greater than the conventional “1U” server height. In such embodiments, fans 919 may generally comprise relatively slow, large diameter cooling fans as compared to fans used in conventional rack configurations. Running larger diameter cooling fans at lower speeds may increase fan lifetime relative to smaller diameter cooling fans running at higher speeds while still providing the same amount of cooling. The sleds are physically shallower than conventional rack dimensions. Further, components are arranged on each sled to reduce thermal shadowing (i.e., not arranged serially in the direction of air flow). As a result, the wider, shallower sleds allow for an increase in device performance because the devices can be operated at a higher thermal envelope (e.g., 250 Watts (W)) due to improved cooling (i.e., no thermal shadowing, more space between devices, more room for larger heat sinks, etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules 920-1 to 920-7, each of which may draw power from an external power source 921. In various embodiments, external power source 921 may deliver alternating current (AC) power to rack 902, and power modules 920-1 to 920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules 920-1 to 920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-mode optical switching infrastructure 914, which may be the same as—or similar to—dual-mode optical switching infrastructure 514 of FIG. 5. In various embodiments, optical connectors contained in MPCMs 916-1 to 916-7 may be designed to couple with counterpart optical connectors contained in MPCMs of inserted sleds to provide such sleds with optical signaling connectivity to dual-mode optical switching infrastructure 914 via respective lengths of optical cabling 922-1 to 922-7. In some embodiments, each such length of optical cabling may extend from its corresponding MPCM to an optical interconnect loom 923 that is external to the sled spaces of rack 902. In various embodiments, optical interconnect loom 923 may be arranged to pass through a support post or other type of load-bearing element of rack 902. The optical interconnect loom 923 may include cabling conduit and other cable management hardware, such as cable rings, cable panels, cable brackets, pass through panels, and so forth The embodiments are not limited in this context. These cable management features can save time because inserted sleds connect to an optical switching infrastructure via MPCMs, the resources typically spent in manually configuring the rack cabling to accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representative of a sled designed for use in conjunction with rack 902 of FIG. 9 according to some embodiments. Sled 1004 may feature an MPCM 1016 that comprises an optical connector 1016A and a power connector 1016B, and that is designed to couple with a counterpart MPCM of a sled space in conjunction with insertion of MPCM 1016 into that sled space. Coupling MPCM 1016 with such a counterpart MPCM may cause power connector 1016 to couple with a power connector comprised in the counterpart MPCM. This may generally enable physical resources 1005 of sled 1004 to source power from an external source, via power connector 1016 and power transmission media 1024 that conductively couples power connector 1016 to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry 1026. Dual-mode optical network interface circuitry 1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-mode optical switching infrastructure 914 of FIG. 9. In some embodiments, dual-mode optical network interface circuitry 1026 may be capable both of Ethernet protocol communications and of communications according to a second, high-performance protocol. In various embodiments, dual-mode optical network interface circuitry 1026 may include one or more optical transceiver modules 1027, each of which may be capable of transmitting and receiving optical signals over each of one or more optical channels. The embodiments are not limited in this context.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a given rack may cause optical connector 1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode optical network interface circuitry 1026, via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 may communicate with the physical resources 1005 of sled 1004 via electrical signaling media 1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250 W), as described above with reference to FIG. 9, in some embodiments, a sled may include one or more additional features to facilitate air cooling, such as a heatpipe and/or heat sinks arranged to dissipate heat generated by physical resources 1005. It is worthy of note that although the example sled 1004 depicted in FIG. 10 does not feature an expansion connector, any given sled that features the design elements of sled 1004 may also feature an expansion connector according to some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As reflected in FIG. 11, a physical infrastructure management framework 1150A may be implemented to facilitate management of a physical infrastructure 1100A of data center 1100. In various embodiments, one function of physical infrastructure management framework 1150A may be to manage automated maintenance functions within data center 1100, such as the use of robotic maintenance equipment to service computing equipment within physical infrastructure 1100A. In some embodiments, physical infrastructure 1100A may feature an advanced telemetry system that performs telemetry reporting that is sufficiently robust to support remote automated management of physical infrastructure 1100A. In various embodiments, telemetry information provided by such an advanced telemetry system may support features such as failure prediction/prevention capabilities and capacity planning capabilities. In some embodiments, physical infrastructure management framework 1150A may also be configured to manage authentication of physical infrastructure components using hardware attestation techniques. For example, robots may verify the authenticity of components before installation by analyzing information collected from a radio frequency identification (RFID) tag associated with each component to be installed. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center 1100 may comprise an optical fabric 1112, which may include a dual-mode optical switching infrastructure 1114. Optical fabric 1112 and dual-mode optical switching infrastructure 1114 may be the same as—or similar to—optical fabric 412 of FIG. 4 and dual-mode optical switching infrastructure 514 of FIG. 5, respectively, and may provide high-bandwidth, low-latency, multi-protocol connectivity among sleds of data center 1100. As discussed above, with reference to FIG. 1, in various embodiments, the availability of such connectivity may make it feasible to disaggregate and dynamically pool resources such as accelerators, memory, and storage. In some embodiments, for example, one or more pooled accelerator sleds 1130 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of accelerator resources—such as co-processors and/or field-programmable gate arrays (FPGAs), for example—that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storage sleds 1132 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of storage resources that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage sleds 1132 may comprise pools of storage devices such as solid-state drives (SSDs), hard disk drives (HDD), hard drive, disk drive, fixed disk drives, and so forth. In various embodiments, one or more high-performance processing sleds 1134 may be included among the physical infrastructure 1100A of data center 1100. In some embodiments, high-performance processing sleds 1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250 W or more. In various embodiments, any given high-performance processing sled 1134 may feature an expansion connector 1117 that can accept a multi-level memory expansion sled, such that the memory that is locally available to that high-performance processing sled 1134 is disaggregated from the processors and first level memory comprised on that sled. In some embodiments, such a high-performance processing sled 1134 may be configured with far memory using an expansion sled that comprises low-latency SSD storage. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or storage resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps, for example, remote resources connected through a single or two switches, away in the spine-leaf network architecture described above with reference to FIG. 5. The embodiments are not limited in this context.

In various embodiments, one or more layers of abstraction may be applied to the physical resources of physical infrastructure 1100A in order to define a virtual infrastructure, such as a software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure (SDI) 1100B may be allocated to support the provision of cloud services 1140. In various embodiments, particular sets of virtual computing resources 1136 may be grouped for provision to cloud services 1140 in the form of SDI services 1138. Examples of cloud services 1140 may include—without limitation—software as a service (SaaS) services 1142, platform as a service (PaaS) services 1144, and infrastructure as a service (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100B may be conducted using a virtual infrastructure management framework 1150B. In various embodiments, virtual infrastructure management framework 1150B may be designed to implement workload fingerprinting techniques and/or machine-learning techniques in conjunction with managing allocation of virtual computing resources 1136 and/or SDI services 1138 to cloud services 1140. In some embodiments, virtual infrastructure management framework 1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework 1150C may be implemented in order to provide quality of service (QoS) management capabilities for cloud services 1140. The embodiments are not limited in this context.

FIG. 12 illustrates an example of an operating environment 1200 that may be representative of various embodiments. Operating environment 1200 depicted in FIG. 12 illustrates a cache and system memory arrangement according to some embodiments. Specifically, FIG. 12 shows a memory hierarchy including a two level memory that includes a set of internal processor caches 1220, a first level memory 1221, which may include both on-package cache(s) 1206 and off-package caches 1207-1209, and a second level memory 1222. In some embodiments, first level memory 1221 may operate as a cache for second level memory 1222. One particular type of memory which may be used for second-level memory 1222 in some embodiments may include non-volatile random access memory (“NVRAM”). One particular type of storage device that may be used for second-level memory 1222 in some embodiments may include a storage device operable to communicate via non-volatile memory express (“NVMe”), such as an NVMe-compatible SSD.

The second level memory 1222 of some embodiments may be implemented with NVRAM, but is not necessarily limited to any particular memory technology. Second level memory 1222 is distinguishable from other instruction and data memory/storage technologies in terms of its characteristics and/or its application in the memory/storage hierarchy. For example, second level memory 1222 is different from

-   -   (2) static random access memory (SRAM) which may be used for         level 0 and level 1 internal processor caches 1201 a-b, 1202         a-b, 1203 a-b, 1203 a-b, and 1204 a-b dedicated to each of the         processor cores 1201-1204, respectively, and lower level cache         (LLC) 1205 shared by the processor cores;     -   (3) dynamic random access memory (DRAM) configured as a cache         1206 internal to the processor 1250 (e.g., on the same die as         the processor 1250) and/or configured as one or more caches         1207-1209 external to the processor (e.g., in the same or a         different package from the processor 1250); and     -   (4) FLASH memory/magnetic disk/optical disc applied as mass         storage (not shown); and     -   (5) memory such as FLASH memory or other read only memory (ROM)         applied as firmware memory (which can refer to boot ROM, BIOS         Flash, and/or TPM Flash) (not shown).

In some embodiments, second level memory 1222 may be used as instruction and data storage that is directly addressable by processor 1250 (for instance, as byte addressable random accessible non-volatile memory) and is able to sufficiently keep pace with the processor 1250 in contrast to block addressable memory or volatile memory (for instance, FLASH, SDRAM, DRAM, magnetic disk, optical disc, and/or the like) applied as mass storage. Moreover, as discussed above and described in detail below, second level memory 1222 may be placed on a memory bus and may communicate directly with a memory controller that, in turn, communicates directly with processor 1250.

Second level memory 1222 may be combined with other instruction and data storage technologies (e.g., DRAM) to form hybrid memories (also known as co-locating, for example, byte addressable random accessible non-volatile memory (for instance, PCM) and volatile memory (for instance, DRAM); first level memory and second level memory; FLASH and DRAM, and/or the like). Note that at least some of the above technologies, including NVRAM, may be used for mass storage instead of, or in addition to, system memory, and need not be random accessible, byte addressable or directly addressable by the processor when applied in this manner.

In some examples, NVRAM may be described as the technology selection for the second level memory 1222. As such, the terms NVRAM, PCM, PCMS, and second level memory may be used interchangeably in the following discussion. However it should be realized, as discussed above, that different technologies may also be utilized for second level memory. Also, that NVRAM is not limited for use as second level memory. Non-limiting examples of NVRAM may include phase change memory (PCM), Phase Change Memory and Switch (PCMS) (the latter being a more specific implementation of the former), byte addressable persistent memory (BPRAM), storage class memory (SCM), universal memory, Ge2Sb2Te5, programmable metallization cell (PMC), resistive memory (RRAM), RESET (amorphous) cell, SET (crystalline) cell, PCME, Ovshinsky memory, ferroelectric memory (also known as polymer memory and poly(N-vinylcarbazole)), ferromagnetic memory (also known as Spintronics, SPRAM (spin-transfer torque RAM)), STRAM (spin tunneling RAM), magnetoresistive memory, magnetic memory, magnetic random access memory (MRAM), and Semiconductor-oxide-nitride-oxide-semiconductor (SONOS, also known as dielectric memory)

First level 1221 is an intermediate level of memory communicatively coupled to second level memory 1222 that has lower read/write access latency relative to second level memory and/or more symmetric read/write access latency (i.e., having read times which are roughly equivalent to write times). In some embodiments, the first level memory 1221 has significantly lower write latency than the second level memory 1222 but similar (e.g., slightly lower or equal) read latency; for instance the first level memory 1221 may be a volatile memory such as volatile random access memory and may comprise a DRAM or other high speed capacitor-based memory. Embodiments are not limited to these specific memory types. Additionally, first level memory 1221 may have a relatively lower density and/or may be more expensive to manufacture than the second level memory 1222.

In one embodiment, first level memory 1221 is configured between the second level memory 1222 and the internal processor caches 1220. In some of the embodiments described below, first level memory 1221 is configured as one or more memory-side caches (MSCs) 1207-1209 to mask the performance and/or usage limitations of the second level memory including, for example, read/write latency limitations and memory degradation limitations. In these implementations, the combination of the MSC 1207-1209 and second level memory 1222 operates at a performance level which approximates, is equivalent or exceeds a system which uses only DRAM as system memory. Although shown as a “cache” in FIG. 12, the first level memory 1221 may include modes in which it performs other roles, either in addition to, or in lieu of, performing the role of a cache.

First level memory 1221 can be located on the processor die (as cache(s) 1206) and/or located external to the processor die (as caches 1207-1209) (e.g., on a separate die located on the CPU package, located outside the CPU package with a high bandwidth link to the CPU package, for example, on a memory dual in-line memory module (DIMM), a riser/mezzanine, or a computer motherboard). First level memory 1221 may be communicatively coupled to processor 1250 using a single or multiple high bandwidth links, such as DDR or other transactional high bandwidth links (as described in detail below).

FIG. 12 illustrates how various levels of caches 1201-1209 are configured with respect to a system physical address (SPA) space 1216-1219 in some embodiments. As mentioned, this embodiment comprises a processor 1250 having one or more cores 1201-1204, with each core having its own dedicated upper level cache (L0) 1201 a-1204 a and mid-level cache (MLC) (L1) cache 1201 b-1204 b. The processor 1250 also includes a shared LLC 1205. The operation of these various cache levels are well understood and will not be described in detail here.

The caches 1207-1209 illustrated in FIG. 12 may be dedicated to a particular system memory address range or a set of non-contiguous address ranges. For example, cache 1207 is dedicated to acting as an MSC for system memory address range #1 1216 and caches 1208 and 1209 are dedicated to acting as MSCs for non-overlapping portions of system memory address ranges #2 1217 and #3 1218. The latter implementation may be used for systems in which the SPA space used by the processor 1250 is interleaved into an address space used by the caches 1207-1209 (e.g., when configured as MSCs). In some embodiments, this latter address space is referred to as a memory channel address (MCA) space. In one embodiment, the internal caches 1201 a-1206 perform caching operations for the entire SPA space.

System memory as used herein is memory which is visible to and/or directly addressable by software executed on the processor 1250; while the cache memories 1201 a-1209 may operate transparently to the software in the sense that they do not form a directly-addressable portion of the system address space, but the cores may also support execution of instructions to allow software to provide some control (configuration, policies, hints, etc.) to some or all of the cache(s). The subdivision of system memory into regions 1216-1219 may be performed manually as part of a system configuration process (e.g., by a system designer) and/or may be performed automatically by software.

In one embodiment, system memory regions 1216-1219 may be implemented using second level memory (e.g., non-volatile memory, including phase-change memory (PCM)) and, in some embodiments, first level memory configured as system memory. In some embodiments, system memory regions may be implemented using second level memory that includes byte addressable non-volatile memory and first level memory that includes volatile memory, with the byte addressable non-volatile memory being slower than the volatile memory System memory address range #4 represents an address range which is implemented using a higher-speed memory such as a higher-speed volatile memory (for instance, DRAM) which may be a first level memory configured in a system memory mode (as opposed to a caching mode).

FIG. 13 illustrates an example of an operating environment 1300 that may be representative of various embodiments. Operating environment 1300 depicted in FIG. 13 illustrates an embodiment of a two-level memory system used in conjunction with at least one embodiment employing a two-level memory (2LM). In some embodiments, the 2LM may be implemented as a system memory or a main memory. In some embodiments, the memory system depicted in FIG. 13 may be implemented as a three-level memory (3LM) storage architecture (not shown). In at least one embodiment, system 1300 includes a processor 1301 and a main memory 1310 that includes a far memory 1330 and a portion of near memory 1320.

In some embodiments, processor 1301 includes an execution core 1302. In some embodiments, execution core 1302 includes a front end 1304, an execution pipeline 1306, and a core cache 1312. In some embodiments, front end 1304 may be responsible for pre-fetching instructions, perhaps in conjunction with an instruction pointer (not depicted), decoding instructions, and pre-fetching of data corresponding to instruction operands that are available. In some embodiments, front end 1304 may include a prefetch manager 1305, instruction prefetcher 1307, data prefetcher, and/or instruction decode unit 1309. Prefetch manager 1305 may be configured to determine memory access information for workloads to be executed by processor 1301 according to some embodiments. For example, prefetch manager 1305 may operate to monitor workloads being executed by processor 1301 to determine memory access information associated with the workloads. In another example, prefetch manager 1305 may determine whether a workload includes memory access information, such as in a prefetch header. These functions and other functions of the prefetch manager 1305 according to some embodiments are described in more detail below.

The instruction prefetcher 1307 may be configured to prefetch instructions and/or other data. In some embodiments, the instruction prefetcher 1307 may operate to prefetch instructions, memory pages, and/or other data based on the memory access information provided by the prefetch manager 1305. In some embodiments, the prefetch manager 1305 may be implemented in hardware, software, and/or a combination thereof. In various embodiments, the prefetch manager 1305 may be a component of instruction prefetcher 1307.

In some embodiments, the prefetch manager 1307 may provide the prefetched data to an instruction decode unit 1309 to decode the data. In various embodiments, the decoded data, for instance, a decoded instruction, may be provided to an execution pipeline 1306. In at least one embodiment, execution pipeline 1306 may be responsible for scheduling instructions for execution, executing instructions in one or more execution ports (not shown in FIG. 13) and retiring the results of the instructions. For memory access instructions, instruction execution may include accessing a data cache referred to in FIG. 13 as core cache 1312. While in some embodiments processor 1301 includes just one execution core 1302, processor 1301 may include multiple execution cores 1302.

The data prefetcher 1308 may be configured to prefetch data. In some embodiments, the data prefetcher 1308 may operate to prefetch data based on the memory access information provided by the prefetch manager 1305. In various embodiments, the prefetch manager 1305 may be a component of data prefetcher 1308. In some embodiments, data prefetcher 1308 may be operative to prefetch data to increase the speed and/or efficiency of data fetches.

In at least one embodiment, as suggested by its name, uncore region 1316 of processor 1301 refers generally to elements of processor 1301 not directly associated with the execution core 1302 of processor 1301. In some embodiments, uncore region 1316 encompasses elements of processor 1301 that may interface execution core 1302 with system memory, input/output (I/O) devices, and so forth. In some embodiments, uncore 1316 may communicate with chipset devices (not depicted) that provide interfaces for various types of I/O devices. Although in some embodiments, the functionality depicted may be illustrated as being implemented in uncore region 1316 of processor 1301, other embodiments may delegate analogous functionality to a chipset device. Similarly, while in some embodiments, uncore region 1316 may suggest that some functionality is located in a chipset device, other embodiments may incorporate analogous functionality into uncore region 1316.

In some embodiments, processor 1301 includes a 2LM engine 1340 that coordinates near memory 1320 and far memory 1330. In some embodiments, 2LM engine 1340 communicates with a near memory controller (NMC) 1325 that provides memory control functions for near memory 1320. In at least one embodiment, 2LM engine 1340 also communicates with a far memory controller (FMC) 1335 that provides memory control functions for far memory 1330. In some embodiments, 2LM engine 1340 beneficially maintains near memory 1320 as a combination of a conventional cache memory and a specially allocated portion, referred to herein as a pin buffer, that comprises a portion of the addressable memory space visible to the operating system. In these embodiments, a majority of the system memory space visible to the operating system is represented by far memory 1330 while a small portion of the system memory includes a portion of near memory 1320. In some embodiments, a remaining portion of near memory 1320 functions as a far memory cache that is not visible to the operating system, but stores copies of portions of far memory 1330 to improve performance and decrease memory access latency.

In some embodiments, because near memory 1320 acts as a cache of far memory 1330, the 2LM engine 1340 may be used to execute data pre-fetching or similar cache processes in combination with prefetch manager 1305 and/or instruction prefetcher 1307.

FIG. 14 illustrates an example of an operating environment 1400 that may be representative of various embodiments. Operating environment 1400 depicted in FIG. 14 illustrates a direct cache model 2LM implementation. In some embodiments, far memory 1410 may include one or more dual in-line memory modules (DIMMs), for instance, with byte addressable write-in-place memory devices. In some embodiments, a DIMM may include a standard JEDEC NVDIMM, such as specified in DDR NVDIMM-N Design Standard (Revision 1.0). Non-limiting examples of byte addressable write-in-place memory devices may include future generation nonvolatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.

As shown in FIG. 14, far memory 1410 may have segments 1420 a-1420 e having cache lines 1425 a-e. A memory controller (not shown) may report a size of the far memory 1410 as a system physical address (SPA) region to an operating system (OS) as OS visible memory. In some embodiments, near memory 1405 may include DIMM and/or high band width (HBM) memory modules. In various embodiments, far memory 1410 may be cached by near memory 1405 and may use a direct replacement model. In general, near memory 1405 may be configured to have better performance as compared with far memory 1410.

When a workload, for instance, an application, accesses segment 1420 a (i.e., segment 0-1), corresponding cache line 1425 a may be copied to near memory 1405 cache line (or page) 1415 and a response is provided to the workload. If a write occurs to cache line 1425 a, the write may go or may also go to cache line 1415 of near memory 1405. If far memory 1410 address 1420 b is accessed, near memory evicts cache line 1415 for far memory 1410 cache line 1425 a and copies cache line 1425 to cache line 1415. Accordingly, the process of which cache line 1425 a-e resides in cache line 1415 is hardware controlled, for example, based on workload access to far memory 1410 pages. Accordingly, if a workload accesses page 1 from far memory 1410 region 1420 a and then page 1 from far memory 1410 region 1420 b, overall memory access time for the workload may be increased resulting in poor performance, particularly for workloads that access non-contiguous memory regions.

FIG. 15 illustrates an example of an operating environment 1500 that may be representative of various embodiments. Operating environment 1500 depicted in FIG. 15 illustrates a workload memory access monitoring process according to some embodiments. As shown in FIG. 15, a processor 1530 may include prefetch manager 1550 configured to monitor memory accesses within a system memory 1540. In some embodiments, processor 1530 may implement or may access information resulting from a feedback loop operative to monitor workload behavior. A near memory 1505 may include cache lines (or pages) 1515 a-n and a far memory 1510 may include regions 1520 a-e having cache lines 1525 a-e. In general, near memory 1505 may include high performance memory and far memory 1510 may include low performance memory compared with near memory 1505. In some embodiments, operating environment 1500 may be or may include a virtual machine VM. Accordingly, in some embodiments, processor 1530 may include a virtual processor of a VM.

In some embodiments, for example, a hypervisor (not shown) of a VM may manage memory access by workloads being executed by processor 1530. For instance, cache lines 1525 a-e of memory regions 1520 a-e of far memory 1510 access by a workload may be cached as cache lines 1515 a-n of near memory 1505. In addition, low access cache pages 1515 a-n of near memory 1505 may be evicted to far memory 1510 and high access far memory 1510 may be brought into near memory 1505. In some embodiments, far memory 1510 may be visible to the OS, while near memory 1505 may not be visible to the OS and may be visible to the hypervisor.

Prefetch manager 1550, for example, as operated by the hypervisor, may monitor memory accesses of memory system 1540 by workloads executing on processor 1530. For example, prefetch manager 1550 may access workload execution information generated as part of a feedback loop configured to monitor workload behavior. Non-limiting examples of memory accesses may include a workload accessing far memory 1510 and/or near memory 1505, writing of a cache line 1525 a-e to near memory 1505, and/or eviction of a cache line 1515 a-n from near memory. Prefetch manager 1550 may generate memory access information 1570 based on the memory accesses of a workload. In various embodiments, memory access information 1570 may include information relating to memory access of a workload including, without limitation, far memory requests, order of memory requests, frequency of memory requests, a requested memory page, a requested cache line, a workload state during a memory request, and/or the like. In general, memory access information 1570 may indicate a memory access pattern for a workload.

In some embodiments, operating environment 1500 may include a prefetch watcher 1555 component, for instance, as part of prefetch manager 1550. Although FIG. 15 depicts prefetch watcher 1555 as an element of prefetch manager 1550, embodiments are not so limited as prefetch watcher 1555 may be an individual element, a part of a different component, and/or a combination thereof. In some embodiments, prefetch watcher 1555 may be or may include a compiler and/or linker. In some embodiments, prefetch watcher 1555 may be implemented in hardware, software, and/or a combination thereof. In some embodiments, prefetch watcher 1555 may be operated by a hypervisor (not shown) and/or a virtual machine (not shown). In various embodiments, prefetch watcher 1555 may operate to determine memory information, such as near memory size, far memory size, memory performance characteristics, cache placement policies, and/or the like. The memory information may be used to create instruction prefetches and/or data prefetches according to some embodiments, for instance, in combination with the memory access information 1570.

In some embodiments, memory access information 1570 and/or a portion thereof may be stored in memory, such as in an access pattern data store 1560. In various embodiments, access pattern data store 1560 may include a database, table, and/or other data structure or format. In various embodiments, access pattern data store 1560 and/or portions thereof may be stored locally, for example, at a processor-level cache or other memory unit. In various embodiments, access pattern data store 1560 and/or portions thereof may be stored at a system-level memory, such as at a POD-level.

In various embodiments, each workload may include an identifier and access pattern data store 1560 may include a record for each workload that includes memory access information 1570 associated with the workload. In another example, workloads may be categorized into various types (for example, networking applications, user applications, a system application, an OS application, a memory application, a thread, an application thread, an OS thread, and/or the like) and access pattern data store 1560 may include records having memory access information 1570 associated with the various types. In some embodiments, if a new workload is encountered that does not have an associated access pattern, the new workload may be initially associated with memory access information 1570 of a related application. In some embodiments, a workload may be associated with memory access information 1570 having a single memory access pattern. In some embodiments, a workload may be associated with memory access information 1570 having a plurality of memory access patterns. In such embodiments, each memory access pattern may be associated with one or more workload characteristics that may determine which memory access pattern should be used for a particular execution. Non-limiting examples of workload characteristics may include prior workloads, subsequent workloads, number of executions of workload, applications associated with workload, computing devices associated with workload, users associated with workload, workload requester, and/or the like.

Instruction prefetcher 1580 may operate to prefetch instructions and/or other data from far memory 1510 to be cached in near memory 1505. In some embodiments, hypervisor, for instance, via instruction prefetcher 1580, may access memory access information 1570 responsive to execution of a workload. The hypervisor may use the memory access pattern of the workload indicated by the corresponding memory access information 1570 to prefetch data from far memory 1510 for caching in near memory 1505. For example, instruction prefetcher 1580 may provide prefetch manager with an identifier for a workload being executed or to be executed by processor 1530. Prefetch manager 1550 may look up the identified workload in the access pattern data store to determine memory access information (for instance, previous, existing, or “historical” memory access information) associated with the workload. If prefetch manager locates historical memory access information associated with the identified workload, prefetch manager may provide corresponding memory access information 1570 to instruction prefetcher 1580. When instruction prefetcher 1580 initially accesses far memory 1510 during execution of the identified workload, instruction prefetcher may obtain all or at least a portion of the data (for instance, cache lines 1525 a-e) from far memory for caching in near memory 1505.

Accordingly, historical memory access information 1570 associated with a workload may be used to improve performance of the workload during subsequent executions. In addition, a need for a direct mapped cache, and, therefore, any required hardware/software (for instance, a 2LM hardware engine to implement a direct mapped cache in main memory 1310) may be eliminated.

FIG. 16 illustrates an example of an operating environment 1600 that may be representative of various embodiments. Operating environment 1600 depicted in FIG. 16 illustrates a workload memory access monitoring process according to some embodiments. As shown in FIG. 16, a processor 1630 may include prefetch manager 1650 configured to access workloads 1630 a-n. A workload 1630 a-n may include various payloads, such as workload data 1632 and/or workload code 1636. In some embodiments, a payload 1630 a-n may include a prefetch header 1634 a-n. In various embodiments, prefetch header 1634 a-n may include memory access information 1660 configured according to some embodiments. For example, in various embodiments, a workload 1630 a-n may define a prefetch data structure that, for instance, may be generated during a compilation process and/or execution of a workload 1630 a-n. In some embodiments in which workload 1630 a-n may be formed of binary encoded instructions, prefetch header 1634 a-n may be included in workload 1630 a-n, for example, in binary code prior to the instructions.

A hypervisor monitors, for example, via workload manager 1650, for prefetch headers 1634 a-n of workloads being executed and/or to be executed. In some embodiments, workload manager 1650 may locate and decode, as necessary, memory access information 1660 in prefetch header 1634 a-n. In some embodiments, one or more packets may be generated to implement workloads 1630 a-n. In various embodiments, payloads 1630 a-n may be included as payload packet data of packets used to implement workloads 1630 a-n may. In some embodiments, prefetch headers 1634 a-n may include or may be formed in a header of packet data used to implement a workload.

Workload manager 1650 may provide memory access information 1660 to instruction prefetcher 1670 to prefetch data for workload 1630 a-n according to some embodiments. In some embodiments, prefetch may be performed in a hardware specific mechanism, for instance, for a 2LM or 3LM memory implementation. In some embodiments, prefetch may not be performed in a hardware specific mechanism.

In various embodiments, workload 1630 a-n may provide its own memory access information 1660, such as a memory access pattern and/or the like as part of a workload header or other data structure. In some embodiments, prefetch header 1634 a-n may be pre-processed by the hypervisor and/or OS loader, for instance, via workload manager 1650, to perform data prefetch to a near memory to improve workload performance. In some embodiments, workload data 1632 and/or another element may indicate that data is for one-time use. Accordingly, the nature of the one-time use data may be provided to instruction prefetcher 1670 via memory access information 1660 so that the one-time data may not be cached by instruction prefetcher 1670.

In some embodiments, workload 1630 a-n may have a general prefetch header 1634 a-n for the life of the workload 1630 a-n. In some embodiments, workload 1630 a-n may include modules or sub-modules (for example, a library, dynamic link library (DLL), and/or the like) which may contain their own prefetch information. In some embodiments, memory access information 1660 may be generated dynamically. In such embodiments, workload 1630 a-n may include a prefetch activated element configured to indicate that the prefetch data (for example, memory access information) is activated or otherwise ready, indicate a life span of the prefetch data, and/or the like.

FIG. 17 illustrates an embodiment of logic flow 1700. Logic flow 1700 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, logic flow 1700 may illustrate operations performed by a processor and/or hypervisor, as discussed herein. However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein.

At block 1702, logic flow 1700 may monitor workload memory accesses. For instance, a hypervisor of a VM, such as via prefetch manager 1550, may monitor accesses of far memory 1510 and/or near memory 1505 by a workload being executed by processor 1530. Logic flow may determine a workload memory access pattern at block 1704. For example, prefetch manager 1550 may determine a pattern of memory accesses performed during execution of a workload including, without limitation, regions of far memory 1510 accesses, order of memory requests, data requested from and/or written to memory, instructions performed and/or requested, and/or the like. Such information may provide a memory and/or data usage pattern for a workload.

At block 1706, logic flow 1700 may store the workload memory access pattern as memory access information in an access pattern data store. For example, memory access information 1570 may include information relating to memory access of a workload including, without limitation, far memory requests, order of memory requests, frequency of memory requests, and/or the like. In general, memory access information 1570 may indicate a memory access pattern for a workload. In various embodiments, memory access information 1570 and/or a portion thereof may be stored in memory, such as in an access pattern data store 1560. In various embodiments, access pattern data store 1560 may include a database, table, and/or other data structure or format. In various embodiments, access pattern data store 1560 and/or portions thereof may be stored locally, for example, at a processor-level cache and/or at a system-level memory.

FIG. 18 illustrates an embodiment of logic flow 1800. Logic flow 1800 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, logic flow 1800 may illustrate operations performed by a processor and/or hypervisor, as discussed herein. However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein.

At block 1802, logic flow 1800 may determine a workload to be executed. For example, a workload may be executed or scheduled to be executed on processor 1530. In some embodiments, a workload may include an identifier, including a unique identifier such that certain workloads may be identified by processor 1530 and/or components thereof, such as prefetch manager 1550. Logic flow 1800 may determine whether an access pattern exists for the workload at decision block 1804. For example, prefetch manager may lookup, search, or otherwise determine whether memory access information 1570 having an access pattern exists in access pattern data store 1560.

If memory access information 1570 having an access pattern does exists in access pattern data store 1560, logic flow 1800 ends at block 1806. If memory access information 1570 having an access pattern exists in access pattern data store 1560, logic flow determines memory access information for the workload at block 1808. For example, prefetch manager 1550 may determine an access pattern for the workload based on memory access information 1570 corresponding to the workload. At block 1810, logic flow 1800 may prefetch data for workload according to the memory access pattern. For instance, instruction prefetcher 1580 may fetch data from far memory 1510 for caching in near memory 1505 for a workload based on the memory access pattern associated with the workload.

FIG. 19 illustrates an embodiment of logic flow 1900. Logic flow 1900 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, logic flow 1900 may illustrate operations performed by a processor and/or hypervisor, as discussed herein. However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein.

At block 1902, logic flow 1900 may determine memory access information for a workload. For example, a user may provide memory access information (for instance, via a user interface, providing a database of memory access information accessible by logic flow 1900, and/or the like), and/or a workload 1630 a-n may define a prefetch data structure that, for instance, may be generated during a compilation process and/or execution of a workload 1630 a-n. Logic flow 1900 may generate prefetch header according to memory access information at block 1904. For example, workload 1630 a-n may include prefetch header 1634 a-n that includes memory access information. In some embodiments, workload 1630 a-n may have a general prefetch header 1634 a-n for the life of the workload 1630 a-n. In some embodiments, workload 1630 a-n may include modules or sub-modules (for example, a library, dynamic link library (DLL), and/or the like) which may contain their own prefetch information. In some embodiments, memory access information 1660 may be generated dynamically. At block 1906, logic flow 1900 may provide workload with prefetch header. For example, workload 1630 a-n may be provided to workload manager 1650 of a hypervisor and/or processor 1630. Workload 1630 a-n may include prefetch header 1634 a-n having memory access information.

FIG. 20 illustrates an embodiment of logic flow 2000. Logic flow 2000 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, logic flow 200 may illustrate operations performed by a processor and/or hypervisor, as discussed herein. However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein.

At block 2002, logic flow 2000 may determine a workload to be executed. For example, a workload may be received by a hypervisor and/or processor 1530 for execution. Logic flow 2000 may determine whether the workload includes a prefetch header at determination block 2004. For instance, a hypervisor may monitor, for example, via workload manager 1650, for prefetch headers 1634 a-n of workloads. In some embodiments in which workload 1630 a-n may be formed of binary encoded instructions, prefetch header 1634 a-n may be included in workload 1630 a-n, for example, in binary code prior to the instructions. In some embodiments, prefetch headers 1634 a-n may include or may be formed in a header of packet data used to implement a workload. If the workload does not include a prefetch header at determination block 2004, logic flow 2000 ends at block 2006. If the workload does include a prefetch header at determination block 2004, logic flow 2000 may determine memory access information at block 2008. For example, in some embodiments, workload manager 1650 may locate and decode, as necessary, memory access information 1660 in prefetch header 1634 a-n.

At block 2010, logic flow 2000 may prefetch data for the workload according to the memory access pattern. For instance, instruction prefetcher 1680 may fetch data from a far memory for caching in a near memory for the workload based on the memory access pattern associated with the workload. For example, a memory access pattern for a first workload may indicate that the first workload accesses data in a first region of a second level memory, for instance, after performing a certain instruction. Accordingly, logic flow 2000 may prefetch data from the first region and cache the data in a corresponding first level memory, for instance, responsive to determining that the workload has performed the certain instruction. In another example, a memory access pattern for a second workload may indicate that the second workload requests data from a second region of a second level memory after requesting data from a third level of the second level memory. Accordingly, logic flow 2000 may cache the data in the second region of the second level memory in the first level memory responsive to determining that the workload has accessed the data in the third region of the second level memory (via the second level memory or as cached in the first level memory).

Some embodiments may be described using the expression “one embodiment” or “an embodiment” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Further, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The following include non-limiting examples according to some embodiments:

Example 1 is an apparatus, comprising at least one memory, at least one processor, and logic, at least a portion of the logic comprised in hardware, the logic to determine at least one workload to be executed via the at least one processor, monitor a plurality of memory accesses of the at least one memory by the at least one workload during execution, and generate memory access information for the at least one workload based on the plurality of memory accesses.

Example 2 is the apparatus of Example 1, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 3 is the apparatus of Example 1, the memory access information comprising a plurality of memory access patterns for the at least one workload.

Example 4 is the apparatus of Example 1, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic.

Example 5 is the apparatus of Example 1, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic comprising at least one of a prior workload, a subsequent workload, a number of executions, an associated application, or a workload requester.

Example 6 is the apparatus of Example 1, the logic to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy, and generate a prefetch instruction based on the memory information and the memory access information.

Example 7 is the apparatus of Example 1, the logic to provide the memory access information to an instruction prefetcher.

Example 8 is the apparatus of Example 1, the logic to prefetch data for the at least one workload based on the memory access information.

Example 9 is the apparatus of Example 1, the logic to prefetch data for the at least one workload from at least one far memory for caching in at least one near memory based on the memory access information.

Example 10 is the apparatus of Example 1, the at least one workload comprising at least one process performing a memory operation.

Example 11 is the apparatus of Example 1, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 12 is the apparatus of Example 1, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 13 is the apparatus of Example 1, the logic to determine historical memory access information associated with the at least one workload.

Example 14 is the apparatus of Example 1, the logic to determine a unique identifier associated with the at least one workload, determine historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier, and provide the historical memory access information to an instruction prefetcher.

Example 15 is the apparatus of Example 1, the logic to assign a unique identifier for the at least one workload.

Example 16 is the apparatus of Example 1, the logic to monitor the plurality of memory accesses via a feedback loop operative to monitor behavior of the at least one workload.

Example 17 is the apparatus of Example 1, the logic to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy.

Example 18 is the apparatus of Example 1, the logic to store the memory access information in an access pattern data store.

Example 19 is the apparatus of Example 1, the logic to store the memory access information in an access pattern data store, the access pattern data store arranged at a processor-level cache.

Example 20 is the apparatus of Example 1, the logic to associate a unique identifier for the at least one workload with the memory access information, and store the memory access information in an access pattern data store in a record comprising the unique identifier and the memory access information.

Example 21 is the apparatus of Example 1, the logic to categorize the at least one workload into one of a plurality of types.

Example 22 is the apparatus of Example 1, the logic to categorize the at least one workload into one of a plurality of types, associate the at least one workload with memory access information associated with the one of the plurality of types responsive to a determination that the at least one workload is not associated with historical memory access information.

Example 23 is the apparatus of Example 1, the logic to categorize the at least one workload into one of a plurality of types based on a type of application associated with the at least one workload.

Example 24 is the apparatus of Example 1, the logic to categorize the at least one workload into one of a plurality of types, the plurality of types comprising at least two of a networking application, a user application, a system application, a memory application, a thread, an application thread, or an operating system (OS) thread.

Example 25 is the apparatus of Example 1, the at least one memory comprising one of a two-level memory (2LM) or a three-level memory (3LM).

Example 26 is the apparatus of Example 1, the at least one memory comprising a near memory and a far memory, the near memory operating as a cache of the far memory.

Example 27 is a system, comprising an apparatus according to any of claims 1 to 26, and at least one central processing unit (CPU).

Example 28 is a computer-readable storage medium, comprising a plurality of instructions that, when executed, enable processing circuitry to determine a workload to be executed via at least one processor, monitor a plurality of memory accesses of at least one memory by the at least one workload during execution, and generate memory access information for the at least one workload.

Example 29 is the computer-readable storage medium of Example 28, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 30 is the computer-readable storage medium of Example 28, the memory access information comprising a plurality of memory access patterns for the at least one workload.

Example 31 is the computer-readable storage medium of Example 28, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic.

Example 32 is the computer-readable storage medium of Example 28, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic comprising at least one of a prior workload, a subsequent workload, a number of executions, an associated application, or a workload requester.

Example 33 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy, and generate a prefetch instruction based on the memory information and the memory access information.

Example 34 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to provide the memory access information to an instruction prefetcher.

Example 35 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to prefetch data for the at least one workload based on the memory access information.

Example 36 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to prefetch data for the at least one workload from at least one far memory for caching in at least one near memory based on the memory access information.

Example 37 is the computer-readable storage medium of Example 28, the at least one workload comprising at least one process performing a memory operation.

Example 38 is the computer-readable storage medium of Example 28, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 39 is the computer-readable storage medium of Example 28, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 40 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to determine historical memory access information associated with the at least one workload.

Example 41 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to determine a unique identifier associated with the at least one workload, determine historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier, and provide the historical memory access information to an instruction prefetcher.

Example 42 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to assign a unique identifier for the at least one workload.

Example 43 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to monitor the plurality of memory accesses via a feedback loop operative to monitor behavior of the at least one workload.

Example 44 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy.

Example 45 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to store the memory access information in an access pattern data store.

Example 46 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to store the memory access information in an access pattern data store, the access pattern data store arranged at a processor-level cache.

Example 47 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to store the memory access information as a record in an access pattern data store.

Example 48 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to associate a unique identifier for the at least one workload with the memory access information, and store the memory access information in an access pattern data store in a record comprising the unique identifier and the memory access information.

Example 49 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to categorize the at least one workload into one of a plurality of types.

Example 50 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to categorize the at least one workload into one of a plurality of types, associate the at least one workload with memory access information associated with the one of the plurality of types responsive to a determination that the at least one workload is not associated with historical memory access information.

Example 51 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to categorize the at least one workload into one of a plurality of types based on a type of application associated with the at least one workload.

Example 52 is the computer-readable storage medium of Example 28, comprising a plurality of instructions that, when executed, enable processing circuitry to categorize the at least one workload into one of a plurality of types, the plurality of types comprising at least two of a networking application, a user application, a system application, a memory application, a thread, an application thread, or an operating system (OS) thread.

Example 53 is a method, comprising determining at least one workload to be executed via at least one processor, monitor a plurality of memory accesses of the at least one memory by the at least one workload during execution, and generate memory access information for the at least one workload based on the plurality of memory accesses.

Example 54 is the method of Example 53, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 55 is the method of Example 53, the memory access information comprising a plurality of memory access patterns for the at least one workload.

Example 56 is the method of Example 53, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic.

Example 57 is the method of Example 53, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic comprising at least one of a prior workload, a subsequent workload, a number of executions, an associated application, or a workload requester.

Example 58 is the method of Example 53, comprising determining memory information comprising one or more of memory size, memory performance, or a cache placement policy, and generating a prefetch instruction based on the memory information and the memory access information.

Example 59 is the method of Example 53, comprising providing the memory access information to an instruction prefetcher.

Example 60 is the method of Example 53, comprising prefetching data for the at least one workload based on the memory access information.

Example 61 is the method of Example 53, comprising prefetching data for the at least one workload from at least one far memory for caching in at least one near memory based on the memory access information.

Example 62 is the method of Example 53, the at least one workload comprising at least one process performing a memory operation.

Example 63 is the method of Example 53, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 64 is the method of Example 53, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 65 is the method of Example 53, comprising determining historical memory access information associated with the at least one workload.

Example 66 is the method of Example 53, comprising determining a unique identifier associated with the at least one workload, determining historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier, and providing historical memory access information to an instruction prefetcher.

Example 67 is the method of Example 53, comprising assigning a unique identifier for the at least one workload.

Example 68 is the method of Example 53, comprising monitoring the plurality of memory accesses via a feedback loop operative to monitor behavior of the at least one workload.

Example 69 is the method of Example 53, comprising determining memory information comprising one or more of memory size, memory performance, or a cache placement policy.

Example 70 is the method of Example 53, comprising storing the memory access information in an access pattern data store.

Example 71 is the method of Example 53, comprising storing the memory access information in an access pattern data store, the access pattern data store arranged at a processor-level cache.

Example 72 is the method of Example 53, comprising associating a unique identifier for the at least one workload with the memory access information, storing the memory access information in an access pattern data store in a record comprising the unique identifier and the memory access information.

Example 73 is the method of Example 53, comprising categorizing the at least one workload into one of a plurality of types.

Example 74 is the method of Example 53, comprising categorizing the at least one workload into one of a plurality of types, associating the at least one workload with memory access information associated with the one of the plurality of types responsive to a determination that the at least one workload is not associated with historical memory access information.

Example 75 is the method of Example 53, comprising categorizing the at least one workload into one of a plurality of types based on a type of application associated with the at least one workload.

Example 76 is the method of Example 53, comprising categorizing the at least one workload into one of a plurality of types, the plurality of types comprising at least two of a networking application, a user application, a system application, a memory application, a thread, an application thread, or an operating system (OS) thread.

Example 77 is an apparatus, comprising a workload monitoring means to determine at least one workload to be executed via at least one processor means, and monitor a plurality of memory accesses of at least one memory means by the at least one workload during execution, and a memory access information means to generate memory access information for the at least one workload based on the plurality of memory accesses.

Example 78 is the apparatus of Example 77, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 79 is the apparatus of Example 77, the memory access information comprising a plurality of memory access patterns for the at least one workload.

Example 80 is the apparatus of Example 77, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic.

Example 81 is the apparatus of Example 77, the memory access information comprising a plurality of memory access patterns for the at least one workload, each of the plurality of memory access patterns associated with at least one workload characteristic comprising at least one of a prior workload, a subsequent workload, a number of executions, an associated application, or a workload requester.

Example 82 is the apparatus of Example 77, comprising a memory information means to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy, and an instruction prefetch means to generate a prefetch instruction based on the memory information and the memory access information.

Example 83 is the apparatus of Example 77, the memory access information means to provide the memory access information to an instruction prefetcher.

Example 84 is the apparatus of Example 77, comprising an instruction prefetch means to prefetch data for the at least one workload based on the memory access information.

Example 85 is the apparatus of Example 77, comprising an instruction prefetch means to prefetch data for the at least one workload from at least one far memory for caching in at least one near memory based on the memory access information.

Example 86 is the apparatus of Example 77, the at least one workload comprising at least one process performing a memory operation.

Example 87 is the apparatus of Example 77, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 88 is the apparatus of Example 77, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 89 is the apparatus of Example 77, the memory access information means to determine historical memory access information associated with the at least one workload.

Example 90 is the apparatus of Example 77, comprising a workload monitoring means to determine a unique identifier associated with the at least one workload, the memory access information means to determine historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier, and provide historical memory access information to an instruction prefetch means.

Example 91 is the apparatus of Example 77, comprising a workload monitoring means to assign a unique identifier for the at least one workload.

Example 92 is the apparatus of Example 77, comprising a workload monitoring means to monitor the plurality of memory accesses via a feedback loop operative to monitor behavior of the at least one workload.

Example 93 is the apparatus of Example 77, comprising a memory information means to determine memory information comprising one or more of memory size, memory performance, or a cache placement policy.

Example 94 is the apparatus of Example 77, the memory access information means to store the memory access information in an access pattern data store.

Example 95 is the apparatus of Example 77, the memory access information means to store the memory access information in an access pattern data store, the access pattern data store arranged at a processor-level cache.

Example 96 is the apparatus of Example 77, the workload monitoring means to associate a unique identifier for the at least one workload with the memory access information, and the memory access information means to store the memory access information in an access pattern data store in a record comprising the unique identifier and the memory access information.

Example 97 is the apparatus of Example 77, the workload monitoring means to categorize the at least one workload into one of a plurality of types.

Example 98 is the apparatus of Example 77, the workload monitoring means to categorize the at least one workload into one of a plurality of types, the memory access information means to associate the at least one workload with memory access information associated with the one of the plurality of types responsive to a determination that the at least one workload is not associated with historical memory access information.

Example 99 is the apparatus of Example 77, the workload monitoring means to categorize the at least one workload into one of a plurality of types based on a type of application associated with the at least one workload.

Example 100 is the apparatus of Example 77, the workload monitoring means to categorize the at least one workload into one of a plurality of types, the plurality of types comprising at least two of a networking application, a user application, a system application, a memory application, a thread, an application thread, or an operating system (OS) thread.

Example 101 is the apparatus of Example 77, comprising at least one memory means having one of a two-level memory (2LM) or a three-level memory (3LM).

Example 102 is the apparatus of Example 77, comprising at least one memory means having a near memory and a far memory, the near memory operating as a cache of the far memory.

Example 103 is an apparatus, comprising at least one memory, at least one processor, and logic, at least a portion of the logic comprised in hardware, the logic to determine a workload to be executed via the at least one processor, decode a prefetch header of the at least one workload to determine memory access information, and prefetch data for the at least one workload based on the memory access information.

Example 104 is the apparatus of Example 128, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 105 is the apparatus of Example 128, the logic to provide the memory access information to an instruction prefetcher to prefetch the data.

Example 106 is the apparatus of Example 128, the logic to generate the prefetch header during compilation of the at least one workload.

Example 107 is the apparatus of Example 128, the logic to generate the prefetch header during execution of the at least one workload.

Example 108 is the apparatus of Example 128, the logic to generate the prefetch header dynamically, and provide a signal indicating the prefetch header is activated.

Example 109 is the apparatus of Example 128, the at least one workload comprising a prefetch activated element to indicate whether the memory access information is activated.

Example 110 is the apparatus of Example 128, the at least one workload comprising a prefetch activated element to indicate a life span of the memory access information.

Example 111 is the apparatus of Example 128, the at least one workload comprising at least one module associated with a prefetch header, the at least one module comprising at least one of a library and a dynamic link library.

Example 112 is the apparatus of Example 128, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 113 is the apparatus of Example 128, the at least one workload comprising at least one process performing a memory operation.

Example 114 is the apparatus of Example 128, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 115 is a system, comprising an apparatus according to any of claims 103 to 114, and at least one central processing unit (CPU).

Example 116 is a computer-readable storage medium, comprising a plurality of instructions that, when executed, enable processing circuitry to determine a workload to be executed via at least one processor, decode a prefetch header of the at least one workload to determine memory access information, and prefetch data for the at least one workload based on the memory access information.

Example 117 is the computer-readable storage medium of Example 116, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 118 is the computer-readable storage medium of Example 116, comprising a plurality of instructions that, when executed, enable processing circuitry to provide the memory access information to an instruction prefetcher to prefetch the data.

Example 119 is the computer-readable storage medium of Example 116, comprising a plurality of instructions that, when executed, enable processing circuitry to generate the prefetch header during compilation of the at least one workload.

Example 120 is the computer-readable storage medium of Example 116, comprising a plurality of instructions that, when executed, enable processing circuitry to generate the prefetch header during execution of the at least one workload.

Example 121 is the computer-readable storage medium of Example 116, comprising a plurality of instructions that, when executed, enable processing circuitry to generate the prefetch header dynamically, and provide a signal indicating the prefetch header is activated.

Example 122 is the computer-readable storage medium of Example 116, the at least one workload comprising a prefetch activated element to indicate whether the memory access information is activated.

Example 123 is the computer-readable storage medium of Example 116, the at least one workload comprising a prefetch activated element to indicate a life span of the memory access information.

Example 124 is the computer-readable storage medium of Example 116, the at least one workload comprising at least one module associated with a prefetch header, the at least one module comprising at least one of a library and a dynamic link library.

Example 125 is the computer-readable storage medium of Example 116, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 126 is the computer-readable storage medium of Example 116, the at least one workload comprising at least one process performing a memory operation.

Example 127 is the computer-readable storage medium of Example 116, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 128 is a method, comprising determining a workload to be executed via at least one processor, decoding a prefetch header of the at least one workload to determine memory access information, and prefetching data for the at least one workload based on the memory access information.

Example 129 is the method of Example 128, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 130 is the method of Example 128, comprising providing the memory access information to an instruction prefetcher to prefetch the data.

Example 131 is the method of Example 128, comprising generating the prefetch header during compilation of the at least one workload.

Example 132 is the method of Example 128, comprising generating the prefetch header during execution of the at least one workload.

Example 133 is the method of Example 128, comprising generating the prefetch header dynamically, and providing a signal indicating the prefetch header is activated.

Example 134 is the method of Example 128, the at least one workload comprising a prefetch activated element to indicate whether the memory access information is activated.

Example 135 is the method of Example 128, the at least one workload comprising a prefetch activated element to indicate a life span of the memory access 1.

Example 136 is the method of Example 128, the at least one workload comprising at least one module associated with a prefetch header, the at least one module comprising at least one of a library and a dynamic link library.

Example 137 is the method of Example 128, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 138 is the method of Example 128, the at least one workload comprising at least one process performing a memory operation.

Example 139 is the method of Example 128, the at least one workload comprising at least one of an application, a thread, or communication traffic.

Example 140 is an apparatus , comprising a workload monitoring means to determine a workload to be executed via the at least one processor, and a prefetch data means to decode a prefetch header of the at least one workload to determine memory access information, and prefetch data for the at least one workload based on the memory access information.

Example 141 is the apparatus of Example 140, the memory access information comprising at least one memory access pattern for the at least one workload.

Example 142 is the apparatus of Example 140, the prefetch data means to provide the memory access information to an instruction prefetcher to prefetch the data.

Example 143 is the apparatus of Example 140, comprising a prefetch header means to generate the prefetch header during compilation of the at least one workload.

Example 144 is the apparatus of Example 140, comprising a prefetch header means to generate the prefetch header during execution of the at least one workload.

Example 145 is the apparatus of Example 140, comprising a prefetch header means to generate the prefetch header dynamically, and provide a signal indicating the prefetch header is activated.

Example 146 is the apparatus of Example 140, the at least one workload comprising a prefetch activated element to indicate whether the memory access information is activated.

Example 147 is the apparatus of Example 140, the at least one workload comprising a prefetch activated element to indicate a life span of the memory access information.

Example 148 is the apparatus of Example 140, the at least one workload comprising at least one module associated with a prefetch header, the at least one module comprising at least one of a library and a dynamic link library.

Example 149 is the apparatus of Example 140, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.

Example 150 is the apparatus of Example 140, the at least one workload comprising at least one process performing a memory operation.

Example 151 is the apparatus of Example 140, the at least one workload comprising at least one of an application, a thread, or communication traffic.

It is emphasized that the Abstract of the Disclosure is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the preceding Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are at this moment incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.

What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and/or methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. 

What is claimed is:
 1. An apparatus, comprising: at least one memory; at least one processor; and logic, at least a portion of the logic comprised in hardware, the logic to: determine at least one workload to be executed via the at least one processor, monitor a plurality of memory accesses of the at least one memory by the at least one workload during execution, and generate memory access information for the at least one workload based on the plurality of memory accesses.
 2. The apparatus of claim 1, the memory access information comprising at least one memory access pattern for the at least one workload.
 3. The apparatus of claim 1, the logic to prefetch data for the at least one workload based on the memory access information.
 4. The apparatus of claim 1, the logic to prefetch data for the at least one workload from at least one far memory for caching in at least one near memory based on the memory access information.
 5. The apparatus of claim 1, the at least one workload comprising at least one process performing a memory operation.
 6. The apparatus of claim 1, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.
 7. The apparatus of claim 1, the logic to determine historical memory access information associated with the at least one workload.
 8. The apparatus of claim 1, the logic to: determine a unique identifier associated with the at least one workload, determine historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier, and provide the historical memory access information to an instruction prefetcher.
 9. The apparatus of claim 1, the logic to store the memory access information in an access pattern data store.
 10. The apparatus of claim 1, the logic to: associate a unique identifier for the at least one workload with the memory access information, and store the memory access information in an access pattern data store in a record comprising the unique identifier and the memory access information.
 11. The apparatus of claim 1, the logic to: categorize the at least one workload into one of a plurality of types, associate the at least one workload with memory access information associated with the one of the plurality of types responsive to a determination that the at least one workload is not associated with historical memory access information.
 12. A computer-readable storage medium, comprising a plurality of instructions that, when executed, enable processing circuitry to: determine a workload to be executed via at least one processor; monitor a plurality of memory accesses of at least one memory by the at least one workload during execution; and generate memory access information for the at least one workload based on the plurality of memory accesses.
 13. The computer-readable storage medium of claim 12, the memory access information comprising at least one memory access pattern for the at least one workload.
 14. The computer-readable storage medium of claim 12, comprising a plurality of instructions that, when executed, enable processing circuitry to provide the memory access information to an instruction prefetcher.
 15. The computer-readable storage medium of claim 12, comprising a plurality of instructions that, when executed, enable processing circuitry to prefetch data for the at least one workload based on the memory access information.
 16. The computer-readable storage medium of claim 12, the at least one workload comprising at least one process performing a memory operation.
 17. The computer-readable storage medium of claim 12, the memory access information comprising at least one of a far memory request, a near memory requests, a near memory eviction, an order of a plurality of memory requests, or a requested memory page.
 18. The computer-readable storage medium of claim 12, comprising a plurality of instructions that, when executed, enable processing circuitry to determine historical memory access information associated with the at least one workload.
 19. The computer-readable storage medium of claim 12, comprising a plurality of instructions that, when executed, enable processing circuitry to: determine a unique identifier associated with the at least one workload, determine historical memory access information associated with the at least one workload in an access pattern data store based on the unique identifier; and provide the historical memory access information to an instruction prefetcher.
 20. An apparatus, comprising: at least one memory; at least one processor; and logic, at least a portion of the logic comprised in hardware, the logic to: determine a workload to be executed via the at least one processor, decode a prefetch header of the at least one workload to determine memory access information, and prefetch data for the at least one workload based on the memory access information.
 21. The apparatus of claim 20, the memory access information comprising at least one memory access pattern for the at least one workload.
 22. The apparatus of claim 20, the logic to provide the memory access information to an instruction prefetcher to prefetch the data.
 23. The apparatus of claim 20, the logic to generate the prefetch header during compilation of the at least one workload.
 24. The apparatus of claim 20, the logic to generate the prefetch header during execution of the at least one workload.
 25. The apparatus of claim 20, the logic to: generate the prefetch header dynamically, and provide a signal indicating the prefetch header is activated. 